Motor Evaluation Kit NEVC-MCTRL-100-t01-1.0.0
Firmware for NEVB-MCTRL-100-01 for trapezoidal control of BLDC motors using Hall-effect sensors
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Motor control header file. More...
#include <math.h>
#include <stdint.h>
Go to the source code of this file.
Classes | |
struct | motorflags |
Collection of all motor control flags. More... | |
struct | faultflags |
Collection of all fault flags. More... | |
struct | motorconfigs |
Collection of motor configurations. More... | |
Macros | |
#define | MOTOR_POLES 8 |
Number of poles in the motor. | |
#define | TIM4_FREQ 20000UL |
Desired Switching Frequency for MOSFET Gate Signals. | |
#define | DEAD_TIME 350UL |
Dead Time Specification. | |
#define | HALL_PULLUP_ENABLE FALSE |
Internal Pull-up Resistor Configuration for Hall Sensor Inputs. | |
#define | EMULATE_HALL FALSE |
Emulate Motor Spinning. | |
#define | TIM3_FREQ 200UL |
Desired Electrical Rotational Frequency for "Emulated" Motor. | |
#define | COMMUTATION_TICKS_STOPPED 6000 |
Commutation Stopped Limit. | |
#define | TURN_OFF_MODE TURN_OFF_MODE_COAST |
Turn Off Mode. | |
#define | CURRENT_GAIN 50 |
Current Gain for Current Measurement. | |
#define | CURRENT_SENSE_RESISTOR 2000 |
Current Sense Resistor Value. | |
#define | CURRENT_WARNING_THRESHOLD 408 |
Current Warning Threshold (Register Value) | |
#define | CURRENT_ERROR_THRESHOLD 816 |
Current Error Threshold (Register Value) | |
#define | CURRENT_FAULT_ENABLE FALSE |
Current Fault Enable. | |
#define | SPEED_CONTROL_METHOD SPEED_CONTROL_OPEN_LOOP |
Speed Control Method. | |
#define | SPEED_CONTROLLER_TIME_BASE 200 |
Speed Controller Time Base. | |
#define | SPEED_CONTROLLER_MAX_DELTA 1 |
Speed Controller Maximum Delta (Applicable for Open Loop Control) | |
#define | SPEED_CONTROLLER_MAX_SPEED 400 |
Speed Controller Maximum Speed. | |
#define | PID_K_P 100 |
PID Controller Proportional Gain Constant (Only for Closed Loop) | |
#define | PID_K_I 10 |
PID Controller Integral Gain Constant (Only for Closed Loop) | |
#define | PID_K_D_ENABLE TRUE |
PID Controller Derivative Control Enable Flag (Only for Closed Loop) | |
#define | PID_K_D 0 |
PID Controller Derivative Gain Constant (Only for Closed Loop) | |
#define | GATE_RTOP 1000000 |
Top resistor value in the gate voltage potential divider. | |
#define | GATE_RBOTTOM 71500 |
Bottom resistor value in the gate voltage potential divider. | |
#define | REMOTE_DEBUG_MODE FALSE |
Set the remote debug mode. | |
#define | FALSE 0 |
FALSE constant value. | |
#define | TRUE (!FALSE) |
TRUE constant value, defined to be compatible with comparisons. | |
#define | F_HST 64000000UL |
High-speed system clock frequency. | |
#define | AH_PIN PB6 |
PIN where high side gate PWM for phase A is connected. | |
#define | BH_PIN PC7 |
PIN where high side gate PWM for phase B is connected. | |
#define | CH_PIN PD7 |
PIN where high side gate PWM for phase C is connected. | |
#define | AL_PIN PB5 |
PIN where low side gate PWM for phase A is connected. | |
#define | BL_PIN PC6 |
PIN where low side gate PWM for phase B is connected. | |
#define | CL_PIN PD6 |
PIN where low side gate PWM for phase C is connected. | |
#define | PWM_PATTERN_PORTB ((1 << AH_PIN) | (1 << AL_PIN)) |
Bit pattern of PWM pins placed on PORTB (Phase A). | |
#define | PWM_PATTERN_PORTC ((1 << BH_PIN) | (1 << BL_PIN)) |
Bit pattern of PWM pins placed on PORTC (Phase B). | |
#define | PWM_PATTERN_PORTD ((1 << CH_PIN) | (1 << CL_PIN)) |
Bit pattern of PWM pins placed on PORTD (Phase C). | |
#define | OC_ENABLE_PORTB ((1 << OC4OE3) | (1 << OC4OE2)) |
#define | OC_ENABLE_PORTC ((1 << OC4OE1) | (1 << OC4OE0)) |
#define | OC_ENABLE_PORTD ((1 << OC4OE5) | (1 << OC4OE4)) |
#define | DIRECTION_FORWARD 0 |
Forward direction flag value. | |
#define | DIRECTION_REVERSE 1 |
Reverse direction flag value. | |
#define | DIRECTION_UNKNOWN 3 |
Unknown direction flag value. | |
#define | HALL_PIN PINB |
PIN register for Hall sensor input. | |
#define | H1_PIN PB1 |
Pin where H1 is connected. | |
#define | H2_PIN PB2 |
Pin where H2 is connected. | |
#define | H3_PIN PB3 |
Pin where H3 is connected. | |
#define | ADC_MUX_L_SPEED ADC_MUX_L_ADC4 |
#define | ADC_MUX_H_SPEED ADC_MUX_H_ADC4 |
#define | ADC_MUX_L_CURRENT ADC_MUX_L_ADC7 |
Lower analog channel selection bits (MUX4:0) for motor current measurement. | |
#define | ADC_MUX_H_CURRENT ADC_MUX_H_ADC7 |
High analog channel selection bit (MUX5) for for motor current measurement. | |
#define | ADC_MUX_L_GATEVREF ADC_MUX_L_ADC6 |
Lower analog channel selection bits (MUX4:0) for motor gateVref measurement. | |
#define | ADC_MUX_H_GATEVREF ADC_MUX_H_ADC6 |
High analog channel selection bit (MUX5) for for motor gateVref measurement. | |
#define | ADC_MUX_L_BREF ADC_MUX_L_ADC0 |
Lower analog channel selection bits (MUX4:0) for motor bref measurement. | |
#define | ADC_MUX_H_BREF ADC_MUX_H_ADC0 |
High analog channel selection bit (MUX5) for for motor bref measurement. | |
#define | ADC_PRESCALER ADC_PRESCALER_DIV_8 |
ADC clock pre-scaler used in this application. | |
#define | ADC_REFERENCE_VOLTAGE ADC_REFERENCE_VOLTAGE_VCC |
ADC voltage reference used in this application. | |
#define | ADC_TRIGGER ADC_TRIGGER_TIMER0_OVF |
ADC trigger used in this application. | |
#define | DIRECTION_COMMAND_PIN PD2 |
Pin where direction command input is located. | |
#define | ENABLE_PIN PD0 |
Enable input pin. | |
#define | REMOTE_PIN PD3 |
Remote input pin. | |
#define | SPEED_INPUT_SOURCE_LOCAL 0 |
Speed input source - Local or speed input pin. | |
#define | SPEED_INPUT_SOURCE_REMOTE 1 |
Speed input source - Remote input. | |
#define | FAULT_PIN_1 PD4 |
Fault Pin 1. | |
#define | FAULT_PIN_2 PB4 |
Fault Pin 2. | |
#define | FAULT_PIN_3 PB7 |
Fault Pin 3. | |
#define | WAVEFORM_BLOCK_COMMUTATION 0 |
Waveform constant for block commutation. | |
#define | WAVEFORM_BRAKING 1 |
Waveform status flag for braking. | |
#define | WAVEFORM_UNDEFINED 3 |
Waveform status flag used for coasting. | |
#define | TURN_OFF_MODE_COAST 0 |
TURN_OFF_MODE value for coasting (disabled drivers). | |
#define | TURN_OFF_MODE_BRAKE 1 |
#define | SPEED_CONTROL_OPEN_LOOP 0 |
Speed control selection for open loop control. | |
#define | SPEED_CONTROL_CLOSED_LOOP 1 |
Speed control selection for closed loop control. | |
#define | SPEED_CONTROLLER_MAX_INPUT 255 |
Maximum Speed Reference Input. | |
#define | CHOOSE_TIM4_PRESCALER(tim4Freq) ((tim4Freq) < 15625 ? 4 : ((tim4Freq) < 31250 ? 2 : 1)) |
Macro to choose Timer4 pre-scaler. | |
#define | CHOOSE_DT_PRESCALER(deadTime) |
Macro to choose Timer4 dead time pre-scaler based on the dead time. | |
#define | FORCE_INLINE inline __attribute__((always_inline)) |
Macro for forcing inline expansion of functions. | |
#define | FAST_ACCESS(register_address) __attribute__((address(register_address))) |
Assign a specific memory address to a variable for fast access. | |
#define | PLL_POSTSCALER_OFF ((0 << PLLTM1) | (0 << PLLTM0)) |
PLL Post-scaler - off. | |
#define | PLL_POSTSCALER_DIV_1_0 ((0 << PLLTM1) | (1 << PLLTM0)) |
PLL Post-scaler - division factor 1. | |
#define | PLL_POSTSCALER_DIV_1_5 ((1 << PLLTM1) | (0 << PLLTM0)) |
PLL Post-scaler - division factor 1.5. | |
#define | PLL_POSTSCALER_DIV_2_0 ((1 << PLLTM1) | (1 << PLLTM0)) |
PLL Post-scaler - division factor 1. | |
#define | DT_PRESCALER_DIV_1 ((0 << DTPS41) | (0 << DTPS40)) |
Deadtime generator pre-scaler - division factor 1. | |
#define | DT_PRESCALER_DIV_2 ((0 << DTPS41) | (1 << DTPS40)) |
Deadtime generator pre-scaler - division factor 2. | |
#define | DT_PRESCALER_DIV_4 ((1 << DTPS41) | (0 << DTPS40)) |
Deadtime generator pre-scaler - division factor 4. | |
#define | DT_PRESCALER_DIV_8 ((1 << DTPS41) | (1 << DTPS40)) |
Deadtime generator pre-scaler - division factor 8. | |
#define | TIM1_CLOCK_OFF ((0 << CS12) | (0 << CS11) | (0 << CS10)) |
Timer1 clock - no clock source. | |
#define | TIM1_CLOCK_DIV_1 ((0 << CS12) | (0 << CS11) | (1 << CS10)) |
Timer1 clock - i/o clk with division factor 1. | |
#define | TIM1_CLOCK_DIV_8 ((0 << CS12) | (1 << CS11) | (0 << CS10)) |
Timer1 clock - i/o clk with division factor 8. | |
#define | TIM1_CLOCK_DIV_64 ((0 << CS12) | (1 << CS11) | (1 << CS10)) |
Timer1 clock - i/o clk with division factor 64. | |
#define | TIM1_CLOCK_DIV_256 ((1 << CS12) | (0 << CS11) | (0 << CS10)) |
Timer1 clock - i/o clk with division factor 256. | |
#define | TIM1_CLOCK_DIV_1024 ((1 << CS12) | (0 << CS11) | (1 << CS10)) |
Timer1 clock - i/o clk with division factor 1024. | |
#define | TIM1_CLOCK_EXT_FALLING ((1 << CS12) | (1 << CS11) | (0 << CS10)) |
Timer1 clock - external clock source on Tn pin (falling edge triggered). | |
#define | TIM1_CLOCK_EXT_RISING ((1 << CS12) | (1 << CS11) | (1 << CS10)) |
Timer1 clock - external clock source on Tn pin (rising edge triggered). | |
#define | TIM4_PRESCALER_OFF ((0 << CS43) | (0 << CS42) | (0 << CS41) | (0 << CS40)) |
Timer4 pre-scaler - division factor OFF. | |
#define | TIM4_PRESCALER_DIV_1 ((0 << CS43) | (0 << CS42) | (0 << CS41) | (1 << CS40)) |
Timer4 pre-scaler - division factor 1. | |
#define | TIM4_PRESCALER_DIV_2 ((0 << CS43) | (0 << CS42) | (1 << CS41) | (0 << CS40)) |
Timer4 pre-scaler - division factor 2. | |
#define | TIM4_PRESCALER_DIV_4 ((0 << CS43) | (0 << CS42) | (1 << CS41) | (1 << CS40)) |
Timer4 pre-scaler - division factor 4. | |
#define | ADC_MUX_L_BITS ((1 << MUX4) | (1 << MUX3) | (1 << MUX2) | (1 << MUX1) | (1 << MUX0)) |
Lower ADC channel selection bits (MUX4:0) mask. | |
#define | ADC_MUX_H_BITS (1 << MUX5) |
High ADC channel selection bit (MUX5) mask. | |
#define | ADC_MUX_L_ADC0 ((0 << MUX4) | (0 << MUX3) | (0 << MUX2) | (0 << MUX1) | (0 << MUX0)) |
Lower ADC channel selection bits (MUX4:0) - ADC0/PF0. | |
#define | ADC_MUX_H_ADC0 (0 << MUX5) |
High ADC channel selection bit (MUX5) - ADC0/PF0. | |
#define | ADC_MUX_L_ADC1 ((0 << MUX4) | (0 << MUX3) | (0 << MUX2) | (0 << MUX1) | (1 << MUX0)) |
Lower ADC channel selection bits (MUX4:0) - ADC1/PF1. | |
#define | ADC_MUX_H_ADC1 (0 << MUX5) |
High ADC channel selection bit (MUX5) - ADC1/PF1. | |
#define | ADC_MUX_L_ADC4 ((0 << MUX4) | (0 << MUX3) | (1 << MUX2) | (0 << MUX1) | (0 << MUX0)) |
Lower ADC channel selection bits (MUX4:0) - ADC4/PF4. | |
#define | ADC_MUX_H_ADC4 (0 << MUX5) |
High ADC channel selection bit (MUX5) - ADC4/PF4. | |
#define | ADC_MUX_L_ADC5 ((0 << MUX4) | (0 << MUX3) | (1 << MUX2) | (0 << MUX1) | (1 << MUX0)) |
Lower ADC channel selection bits (MUX4:0) - ADC5/PF5. | |
#define | ADC_MUX_H_ADC5 (0 << MUX5) |
High ADC channel selection bit (MUX5) - ADC5/PF5. | |
#define | ADC_MUX_L_ADC6 ((0 << MUX4) | (0 << MUX3) | (1 << MUX2) | (1 << MUX1) | (0 << MUX0)) |
Lower ADC channel selection bits (MUX4:0) - ADC6/PF6. | |
#define | ADC_MUX_H_ADC6 (0 << MUX5) |
High ADC channel selection bit (MUX5) - ADC6/PF6. | |
#define | ADC_MUX_L_ADC7 ((0 << MUX4) | (0 << MUX3) | (1 << MUX2) | (1 << MUX1) | (1 << MUX0)) |
Lower ADC channel selection bits (MUX4:0) - ADC7/PF7 . | |
#define | ADC_MUX_H_ADC7 (0 << MUX5) |
High ADC channel selection bit (MUX5) - ADC7/PF7. | |
#define | ADC_MUX_L_ADC8 ((0 << MUX4) | (0 << MUX3) | (0 << MUX2) | (0 << MUX1) | (0 << MUX0)) |
Lower ADC channel selection bits (MUX4:0) - ADC8/PD4. | |
#define | ADC_MUX_H_ADC8 (1 << MUX5) |
High ADC channel selection bit (MUX5) - ADC8/PD4. | |
#define | ADC_MUX_L_ADC9 ((0 << MUX4) | (0 << MUX3) | (0 << MUX2) | (0 << MUX1) | (1 << MUX0)) |
Lower ADC channel selection bits (MUX4:0) - ADC9/PD6. | |
#define | ADC_MUX_H_ADC9 (1 << MUX5) |
High ADC channel selection bit (MUX5) - ADC9/PD6. | |
#define | ADC_MUX_L_ADC10 ((0 << MUX4) | (0 << MUX3) | (0 << MUX2) | (1 << MUX1) | (0 << MUX0)) |
Lower ADC channel selection bits (MUX4:0) - ADC10/PD7. | |
#define | ADC_MUX_H_ADC10 (1 << MUX5) |
High ADC channel selection bit (MUX5) - ADC10/PD7. | |
#define | ADC_MUX_L_ADC11 ((0 << MUX4) | (0 << MUX3) | (0 << MUX2) | (1 << MUX1) | (1 << MUX0)) |
Lower ADC channel selection bits (MUX4:0) - ADC11/PB4. | |
#define | ADC_MUX_H_ADC11 (1 << MUX5) |
High ADC channel selection bit (MUX5) - ADC11/PB4. | |
#define | ADC_MUX_L_ADC12 ((0 << MUX4) | (0 << MUX3) | (1 << MUX2) | (0 << MUX1) | (0 << MUX0)) |
Lower ADC channel selection bits (MUX4:0) - ADC12/PB5. | |
#define | ADC_MUX_H_ADC12 (1 << MUX5) |
High ADC channel selection bit (MUX5) - ADC12/PB5. | |
#define | ADC_MUX_L_ADC13 ((0 << MUX4) | (0 << MUX3) | (1 << MUX2) | (0 << MUX1) | (1 << MUX0)) |
Lower ADC channel selection bits (MUX4:0) - ADC13/PB6. | |
#define | ADC_MUX_H_ADC13 (1 << MUX5) |
High ADC channel selection bit (MUX5) - ADC13/PB6. | |
#define | ADC_MUX_L_TEMP_SENSOR ((0 << MUX4) | (0 << MUX3) | (1 << MUX2) | (1 << MUX1) | (1 << MUX0)) |
Lower ADC channel selection bits (MUX4:0) - Temperature Sensor. | |
#define | ADC_MUX_H_TEMP_SENSOR (1 << MUX5) |
High ADC channel selection bit (MUX5) - Temperature Sensor. | |
#define | ADC_MUX_L_1V1 ((1 << MUX4) | (1 << MUX3) | (1 << MUX2) | (1 << MUX1) | (0 << MUX0)) |
Lower ADC channel selection bits (MUX4:0) - 1.1V (Vbandgap). | |
#define | ADC_MUX_H_1V1 (0 << MUX5) |
High ADC channel selection bit (MUX5) - 1.1V (Vbandgap). | |
#define | ADC_MUX_L_0V ((1 << MUX4) | (1 << MUX3) | (1 << MUX2) | (1 << MUX1) | (1 << MUX0)) |
Lower ADC channel selection bits (MUX4:0) - 0V (GND). | |
#define | ADC_MUX_H_0V (0 << MUX5) |
High ADC channel selection bit (MUX5) - 0V (GND). | |
#define | ADC_PRESCALER_DIV_2 ((0 << ADPS2) | (0 << ADPS1) | (0 << ADPS0)) |
ADC pre-scaler - division factor 2. | |
#define | ADC_PRESCALER_DIV_4 ((0 << ADPS2) | (1 << ADPS1) | (0 << ADPS0)) |
ADC pre-scaler - division factor 4. | |
#define | ADC_PRESCALER_DIV_8 ((0 << ADPS2) | (1 << ADPS1) | (1 << ADPS0)) |
ADC pre-scaler - division factor 8. | |
#define | ADC_PRESCALER_DIV_16 ((1 << ADPS2) | (0 << ADPS1) | (0 << ADPS0)) |
ADC pre-scaler - division factor 16. | |
#define | ADC_PRESCALER_DIV_32 ((1 << ADPS2) | (0 << ADPS1) | (1 << ADPS0)) |
ADC pre-scaler - division factor 32. | |
#define | ADC_PRESCALER_DIV_64 ((1 << ADPS2) | (1 << ADPS1) | (0 << ADPS0)) |
ADC pre-scaler - division factor 64. | |
#define | ADC_PRESCALER_DIV_128 ((1 << ADPS2) | (1 << ADPS1) | (1 << ADPS0)) |
ADC pre-scaler - division factor 128. | |
#define | ADC_REFERENCE_VOLTAGE_AREF ((0 << REFS1) | (0 << REFS0)) |
ADC voltage reference - AREF voltage. | |
#define | ADC_REFERENCE_VOLTAGE_VCC ((0 << REFS1) | (1 << REFS0)) |
ADC voltage reference - VCC voltage. | |
#define | ADC_REFERENCE_VOLTAGE_INTERNAL ((1 << REFS1) | (1 << REFS0)) |
ADC voltage reference - internal voltage (2.56V). | |
#define | ADC_TRIGGER_FREE ((0 << ADTS3) | (0 << ADTS2) | (0 << ADTS1) | (0 << ADTS0)) |
ADC auto trigger source - ADC Free Running. | |
#define | ADC_TRIGGER_ANALOG_COMP ((0 << ADTS3) | (0 << ADTS2) | (0 << ADTS1) | (1 << ADTS0)) |
ADC auto trigger source - Analog Comparator. | |
#define | ADC_TRIGGER_INT0 ((0 << ADTS3) | (0 << ADTS2) | (1 << ADTS1) | (0 << ADTS0)) |
ADC auto trigger source - External Interrupt Request 0. | |
#define | ADC_TRIGGER_TIMER0_COMPA ((0 << ADTS3) | (0 << ADTS2) | (1 << ADTS1) | (1 << ADTS0)) |
ADC auto trigger source - Timer/Counter0 Compare Match A. | |
#define | ADC_TRIGGER_TIMER0_OVF ((0 << ADTS3) | (1 << ADTS2) | (0 << ADTS1) | (0 << ADTS0)) |
ADC auto trigger source - Timer/Counter0 Overflow. | |
#define | ADC_TRIGGER_TIMER1_COMPB ((0 << ADTS3) | (1 << ADTS2) | (0 << ADTS1) | (1 << ADTS0)) |
ADC auto trigger source - Timer/Counter1 Compare Match B. | |
#define | ADC_TRIGGER_TIMER1_OVF ((0 << ADTS3) | (1 << ADTS2) | (1 << ADTS1) | (0 << ADTS0)) |
ADC auto trigger source - Timer/Counter1 Overflow. | |
#define | ADC_TRIGGER_TIMER1_CAPT ((0 << ADTS3) | (1 << ADTS2) | (1 << ADTS1) | (1 << ADTS0)) |
ADC auto trigger source - Timer/Counter1 Capture Event. | |
#define | ADC_TRIGGER_TIMER4_OVF ((1 << ADTS3) | (0 << ADTS2) | (0 << ADTS1) | (0 << ADTS0)) |
ADC auto trigger source - Timer/Counter4 Overflow. | |
#define | ADC_TRIGGER_TIMER4_COMPA ((1 << ADTS3) | (0 << ADTS2) | (0 << ADTS1) | (1 << ADTS0)) |
ADC auto trigger source - Timer/Counter4 Compare Match A. | |
#define | ADC_TRIGGER_TIMER4_COMPB ((1 << ADTS3) | (0 << ADTS2) | (1 << ADTS1) | (0 << ADTS0)) |
ADC auto trigger source - Timer/Counter4 Compare Match B. | |
#define | ADC_TRIGGER_TIMER4_COMPD ((1 << ADTS3) | (0 << ADTS2) | (1 << ADTS1) | (1 << ADTS0)) |
ADC auto trigger source - Timer/Counter4 Compare Match D. | |
#define | TIM4_PRESCALER_DIV_PATTERN(tim4Prescaler) |
Timer 4 clock select bits based on pre-scaler value. | |
#define | TIM4_TOP(tim4Freq) (((F_HST / ((uint32_t)tim4Freq * CHOOSE_TIM4_PRESCALER(tim4Freq))) >> 1) - 1) |
#define | TIM4_TOP_MAX 0x03ff |
Maximum top value for Timer 4. | |
#define | DT_PRESCALER_DIV_PATTERN(dtPrescaler) |
Deadtime generator pre-scaler selection bits based on pre-scaler value. | |
#define | DEAD_TIME_HALF(deadTime) (((uint8_t)(ceil((double)deadTime * F_HST / ((double)CHOOSE_DT_PRESCALER(deadTime) * 1000000000))))) |
This value specifies half the dead time in number of clock cycles. Divide by frequency to get duration. | |
#define | TIM3_TOP (((F_CPU / TIM3_FREQ / 3) >> 4) - 1) |
Calculated top value for Timer 3. | |
#define | TIM3_TOP_MAX 0xffff |
Maximum top value for Timer 3. | |
Typedefs | |
typedef struct motorflags | motorflags_t |
Collection of all motor control flags. | |
typedef struct faultflags | faultflags_t |
Collection of all fault flags. | |
typedef struct motorconfigs | motorconfigs_t |
Collection of motor configurations. | |
Motor control header file.
This file contains all defines, typedefs, and prototypes related to the motor control.
Definition in file main.h.