Motor Evaluation Kit NEVC-MCTRL-100-t01-1.0.0
Firmware for NEVB-MCTRL-100-01 for trapezoidal control of BLDC motors using Hall-effect sensors
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Timer 1 (and 3) Clock Select Macros

Timer 1 (and 3) clock selection bits (CS12:0/CS12:0) for TCCR1B/TCCR3B. More...

Collaboration diagram for Timer 1 (and 3) Clock Select Macros:

Macros

#define TIM1_CLOCK_OFF   ((0 << CS12) | (0 << CS11) | (0 << CS10))
 Timer1 clock - no clock source.
 
#define TIM1_CLOCK_DIV_1   ((0 << CS12) | (0 << CS11) | (1 << CS10))
 Timer1 clock - i/o clk with division factor 1.
 
#define TIM1_CLOCK_DIV_8   ((0 << CS12) | (1 << CS11) | (0 << CS10))
 Timer1 clock - i/o clk with division factor 8.
 
#define TIM1_CLOCK_DIV_64   ((0 << CS12) | (1 << CS11) | (1 << CS10))
 Timer1 clock - i/o clk with division factor 64.
 
#define TIM1_CLOCK_DIV_256   ((1 << CS12) | (0 << CS11) | (0 << CS10))
 Timer1 clock - i/o clk with division factor 256.
 
#define TIM1_CLOCK_DIV_1024   ((1 << CS12) | (0 << CS11) | (1 << CS10))
 Timer1 clock - i/o clk with division factor 1024.
 
#define TIM1_CLOCK_EXT_FALLING   ((1 << CS12) | (1 << CS11) | (0 << CS10))
 Timer1 clock - external clock source on Tn pin (falling edge triggered).
 
#define TIM1_CLOCK_EXT_RISING   ((1 << CS12) | (1 << CS11) | (1 << CS10))
 Timer1 clock - external clock source on Tn pin (rising edge triggered).
 

Detailed Description

Timer 1 (and 3) clock selection bits (CS12:0/CS12:0) for TCCR1B/TCCR3B.

Macro Definition Documentation

◆ TIM1_CLOCK_DIV_1

#define TIM1_CLOCK_DIV_1   ((0 << CS12) | (0 << CS11) | (1 << CS10))

Timer1 clock - i/o clk with division factor 1.

Definition at line 801 of file main.h.

◆ TIM1_CLOCK_DIV_1024

#define TIM1_CLOCK_DIV_1024   ((1 << CS12) | (0 << CS11) | (1 << CS10))

Timer1 clock - i/o clk with division factor 1024.

Definition at line 809 of file main.h.

◆ TIM1_CLOCK_DIV_256

#define TIM1_CLOCK_DIV_256   ((1 << CS12) | (0 << CS11) | (0 << CS10))

Timer1 clock - i/o clk with division factor 256.

Definition at line 807 of file main.h.

◆ TIM1_CLOCK_DIV_64

#define TIM1_CLOCK_DIV_64   ((0 << CS12) | (1 << CS11) | (1 << CS10))

Timer1 clock - i/o clk with division factor 64.

Definition at line 805 of file main.h.

◆ TIM1_CLOCK_DIV_8

#define TIM1_CLOCK_DIV_8   ((0 << CS12) | (1 << CS11) | (0 << CS10))

Timer1 clock - i/o clk with division factor 8.

Definition at line 803 of file main.h.

◆ TIM1_CLOCK_EXT_FALLING

#define TIM1_CLOCK_EXT_FALLING   ((1 << CS12) | (1 << CS11) | (0 << CS10))

Timer1 clock - external clock source on Tn pin (falling edge triggered).

Definition at line 811 of file main.h.

◆ TIM1_CLOCK_EXT_RISING

#define TIM1_CLOCK_EXT_RISING   ((1 << CS12) | (1 << CS11) | (1 << CS10))

Timer1 clock - external clock source on Tn pin (rising edge triggered).

Definition at line 813 of file main.h.

◆ TIM1_CLOCK_OFF

#define TIM1_CLOCK_OFF   ((0 << CS12) | (0 << CS11) | (0 << CS10))

Timer1 clock - no clock source.

Definition at line 799 of file main.h.