ADC multiplexer selection bits (MUX5 and MUX4:0) in ADCSRB and ADMUX respectively.
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#define | ADC_MUX_L_BITS ((1 << MUX4) | (1 << MUX3) | (1 << MUX2) | (1 << MUX1) | (1 << MUX0)) |
| Lower ADC channel selection bits (MUX4:0) mask.
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#define | ADC_MUX_H_BITS (1 << MUX5) |
| High ADC channel selection bit (MUX5) mask.
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#define | ADC_MUX_L_ADC0 ((0 << MUX4) | (0 << MUX3) | (0 << MUX2) | (0 << MUX1) | (0 << MUX0)) |
| Lower ADC channel selection bits (MUX4:0) - ADC0/PF0.
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#define | ADC_MUX_H_ADC0 (0 << MUX5) |
| High ADC channel selection bit (MUX5) - ADC0/PF0.
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#define | ADC_MUX_L_ADC1 ((0 << MUX4) | (0 << MUX3) | (0 << MUX2) | (0 << MUX1) | (1 << MUX0)) |
| Lower ADC channel selection bits (MUX4:0) - ADC1/PF1.
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#define | ADC_MUX_H_ADC1 (0 << MUX5) |
| High ADC channel selection bit (MUX5) - ADC1/PF1.
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#define | ADC_MUX_L_ADC4 ((0 << MUX4) | (0 << MUX3) | (1 << MUX2) | (0 << MUX1) | (0 << MUX0)) |
| Lower ADC channel selection bits (MUX4:0) - ADC4/PF4.
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#define | ADC_MUX_H_ADC4 (0 << MUX5) |
| High ADC channel selection bit (MUX5) - ADC4/PF4.
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#define | ADC_MUX_L_ADC5 ((0 << MUX4) | (0 << MUX3) | (1 << MUX2) | (0 << MUX1) | (1 << MUX0)) |
| Lower ADC channel selection bits (MUX4:0) - ADC5/PF5.
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#define | ADC_MUX_H_ADC5 (0 << MUX5) |
| High ADC channel selection bit (MUX5) - ADC5/PF5.
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#define | ADC_MUX_L_ADC6 ((0 << MUX4) | (0 << MUX3) | (1 << MUX2) | (1 << MUX1) | (0 << MUX0)) |
| Lower ADC channel selection bits (MUX4:0) - ADC6/PF6.
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#define | ADC_MUX_H_ADC6 (0 << MUX5) |
| High ADC channel selection bit (MUX5) - ADC6/PF6.
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#define | ADC_MUX_L_ADC7 ((0 << MUX4) | (0 << MUX3) | (1 << MUX2) | (1 << MUX1) | (1 << MUX0)) |
| Lower ADC channel selection bits (MUX4:0) - ADC7/PF7 .
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#define | ADC_MUX_H_ADC7 (0 << MUX5) |
| High ADC channel selection bit (MUX5) - ADC7/PF7.
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#define | ADC_MUX_L_ADC8 ((0 << MUX4) | (0 << MUX3) | (0 << MUX2) | (0 << MUX1) | (0 << MUX0)) |
| Lower ADC channel selection bits (MUX4:0) - ADC8/PD4.
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#define | ADC_MUX_H_ADC8 (1 << MUX5) |
| High ADC channel selection bit (MUX5) - ADC8/PD4.
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#define | ADC_MUX_L_ADC9 ((0 << MUX4) | (0 << MUX3) | (0 << MUX2) | (0 << MUX1) | (1 << MUX0)) |
| Lower ADC channel selection bits (MUX4:0) - ADC9/PD6.
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#define | ADC_MUX_H_ADC9 (1 << MUX5) |
| High ADC channel selection bit (MUX5) - ADC9/PD6.
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#define | ADC_MUX_L_ADC10 ((0 << MUX4) | (0 << MUX3) | (0 << MUX2) | (1 << MUX1) | (0 << MUX0)) |
| Lower ADC channel selection bits (MUX4:0) - ADC10/PD7.
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#define | ADC_MUX_H_ADC10 (1 << MUX5) |
| High ADC channel selection bit (MUX5) - ADC10/PD7.
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#define | ADC_MUX_L_ADC11 ((0 << MUX4) | (0 << MUX3) | (0 << MUX2) | (1 << MUX1) | (1 << MUX0)) |
| Lower ADC channel selection bits (MUX4:0) - ADC11/PB4.
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#define | ADC_MUX_H_ADC11 (1 << MUX5) |
| High ADC channel selection bit (MUX5) - ADC11/PB4.
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#define | ADC_MUX_L_ADC12 ((0 << MUX4) | (0 << MUX3) | (1 << MUX2) | (0 << MUX1) | (0 << MUX0)) |
| Lower ADC channel selection bits (MUX4:0) - ADC12/PB5.
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#define | ADC_MUX_H_ADC12 (1 << MUX5) |
| High ADC channel selection bit (MUX5) - ADC12/PB5.
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#define | ADC_MUX_L_ADC13 ((0 << MUX4) | (0 << MUX3) | (1 << MUX2) | (0 << MUX1) | (1 << MUX0)) |
| Lower ADC channel selection bits (MUX4:0) - ADC13/PB6.
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#define | ADC_MUX_H_ADC13 (1 << MUX5) |
| High ADC channel selection bit (MUX5) - ADC13/PB6.
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#define | ADC_MUX_L_TEMP_SENSOR ((0 << MUX4) | (0 << MUX3) | (1 << MUX2) | (1 << MUX1) | (1 << MUX0)) |
| Lower ADC channel selection bits (MUX4:0) - Temperature Sensor.
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#define | ADC_MUX_H_TEMP_SENSOR (1 << MUX5) |
| High ADC channel selection bit (MUX5) - Temperature Sensor.
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#define | ADC_MUX_L_1V1 ((1 << MUX4) | (1 << MUX3) | (1 << MUX2) | (1 << MUX1) | (0 << MUX0)) |
| Lower ADC channel selection bits (MUX4:0) - 1.1V (Vbandgap).
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#define | ADC_MUX_H_1V1 (0 << MUX5) |
| High ADC channel selection bit (MUX5) - 1.1V (Vbandgap).
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#define | ADC_MUX_L_0V ((1 << MUX4) | (1 << MUX3) | (1 << MUX2) | (1 << MUX1) | (1 << MUX0)) |
| Lower ADC channel selection bits (MUX4:0) - 0V (GND).
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#define | ADC_MUX_H_0V (0 << MUX5) |
| High ADC channel selection bit (MUX5) - 0V (GND).
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ADC multiplexer selection bits (MUX5 and MUX4:0) in ADCSRB and ADMUX respectively.