26#define __AVR_ATmega32U4__ 1
36#ifdef __INTELLISENSE__
37#define ISR(vector) void vector(void)
39#include <avr/interrupt.h>
44#ifdef __INTELLISENSE__
47#include <avr/pgmspace.h>
124#define TIM4_FREQ 20000UL
125#if TIM4_FREQ > 100000UL
126#error "ADVISORY WARNING: TIM4_FREQ should not be set above 100 kHz. If you want to still continue, please uncomment and compile again."
128#if TIM4_FREQ < 7183UL
129#error "ADVISORY WARNING: TIM4_FREQ should not be set below 7183 Hz. If you want to still continue, you'll have to modify the code to allow for a higher pre-scaler value for Timer4."
153#define DEAD_TIME 350UL
155#error "ADVISORY WARNING: DEAD_TIME should not be set below 350 ns. If you want to still continue, please uncomment and compile again."
168#define HALL_PULLUP_ENABLE TRUE
187#define EMULATE_HALL FALSE
203#define TIM3_FREQ 200UL
213#define COMMUTATION_TICKS_STOPPED 6000
226#define TURN_OFF_MODE TURN_OFF_MODE_RAMP
243#define IPHASE_GAIN 20
261#define IPHASE_SENSE_RESISTOR 2500
299#define IBUS_SENSE_RESISTOR 4000
334#define IBUS_WARNING_THRESHOLD 307
373#define IBUS_ERROR_THRESHOLD 410
386#define IBUS_FAULT_ENABLE TRUE
400#define SPEED_CONTROL_METHOD SPEED_CONTROL_OPEN_LOOP
415#define SPEED_CONTROLLER_TIME_BASE 200
436#define SPEED_CONTROLLER_MAX_DELTA 1
457#define SPEED_CONTROLLER_MAX_SPEED 400
514#define PID_K_D_ENABLE TRUE
553#define VBUS_RTOP 100000
573#define VBUS_RBOTTOM 6200
581#define REMOTE_DEBUG_MODE FALSE
601#define F_HST 64000000UL
619#define PWM_PATTERN_PORTB ((1 << AH_PIN) | (1 << AL_PIN))
621#define PWM_PATTERN_PORTC ((1 << BH_PIN) | (1 << BL_PIN))
623#define PWM_PATTERN_PORTD ((1 << CH_PIN) | (1 << CL_PIN))
626#define OC_ENABLE_PORTB ((1 << OC4OE3) | (1 << OC4OE2))
629#define OC_ENABLE_PORTC ((1 << OC4OE1) | (1 << OC4OE0))
632#define OC_ENABLE_PORTD ((1 << OC4OE5) | (1 << OC4OE4))
636#define DIRECTION_FORWARD 0
638#define DIRECTION_REVERSE 1
640#define DIRECTION_UNKNOWN 3
655#define ADC_MUX_L_SPEED ADC_MUX_L_ADC4
658#define ADC_MUX_H_SPEED ADC_MUX_H_ADC4
660#define ADC_MUX_L_IBUS ADC_MUX_L_ADC5
662#define ADC_MUX_H_IBUS ADC_MUX_H_ADC5
664#define ADC_MUX_L_IPHASE_U ADC_MUX_L_ADC1
666#define ADC_MUX_H_IPHASE_U ADC_MUX_H_ADC1
668#define ADC_MUX_L_IPHASE_V ADC_MUX_L_ADC7
670#define ADC_MUX_H_IPHASE_V ADC_MUX_H_ADC7
672#define ADC_MUX_L_IPHASE_W ADC_MUX_L_ADC0
674#define ADC_MUX_H_IPHASE_W ADC_MUX_H_ADC0
676#define ADC_MUX_L_VBUSVREF ADC_MUX_L_ADC6
678#define ADC_MUX_H_VBUSVREF ADC_MUX_H_ADC6
682#define ADC_PRESCALER ADC_PRESCALER_DIV_128
684#define ADC_REFERENCE_VOLTAGE ADC_REFERENCE_VOLTAGE_VCC
686#define ADC_TRIGGER ADC_TRIGGER_TIMER0_OVF
690#define DIRECTION_COMMAND_PIN PD2
692#define ENABLE_PIN PD0
694#define REMOTE_PIN PD3
698#define SPEED_INPUT_SOURCE_LOCAL 0
700#define SPEED_INPUT_SOURCE_REMOTE 1
704#define FAULT_PIN_1 PD4
706#define FAULT_PIN_2 PB4
708#define FAULT_PIN_3 PB7
712#define WAVEFORM_BLOCK_COMMUTATION 0
714#define WAVEFORM_UNDEFINED 3
718#define TURN_OFF_MODE_COAST 0
720#define TURN_OFF_MODE_RAMP 1
724#define SPEED_CONTROL_OPEN_LOOP 0
726#define SPEED_CONTROL_CLOSED_LOOP 1
740#define SPEED_CONTROLLER_MAX_INPUT 255
743#define CHOOSE_TIM4_PRESCALER(tim4Freq) ((tim4Freq) < 15625 ? 4 : ((tim4Freq) < 31250 ? 2 : 1))
761#define CHOOSE_DT_PRESCALER(deadTime) \
762 ((deadTime) <= 234 ? 1 : (deadTime) <= 468 ? 2 \
763 : (deadTime) <= 937 ? 4 \
764 : (deadTime) <= 1875 ? 8 \
778#if defined(__INTELLISENSE__) || defined(__DOXYGEN__)
779#define FORCE_INLINE inline
781#define FORCE_INLINE inline __attribute__((always_inline))
794#if defined(__INTELLISENSE__) || defined(__DOXYGEN__)
795#define FAST_ACCESS(register_address)
797#define FAST_ACCESS(register_address) __attribute__((address(register_address)))
800#ifdef __INTELLISENSE__
810#define sei() ((void)0)
821#define cli() ((void)0)
832#define PLL_POSTSCALER_OFF ((0 << PLLTM1) | (0 << PLLTM0))
834#define PLL_POSTSCALER_DIV_1_0 ((0 << PLLTM1) | (1 << PLLTM0))
836#define PLL_POSTSCALER_DIV_1_5 ((1 << PLLTM1) | (0 << PLLTM0))
838#define PLL_POSTSCALER_DIV_2_0 ((1 << PLLTM1) | (1 << PLLTM0))
848#define DT_PRESCALER_DIV_1 ((0 << DTPS41) | (0 << DTPS40))
850#define DT_PRESCALER_DIV_2 ((0 << DTPS41) | (1 << DTPS40))
852#define DT_PRESCALER_DIV_4 ((1 << DTPS41) | (0 << DTPS40))
854#define DT_PRESCALER_DIV_8 ((1 << DTPS41) | (1 << DTPS40))
865#define TIM1_CLOCK_OFF ((0 << CS12) | (0 << CS11) | (0 << CS10))
867#define TIM1_CLOCK_DIV_1 ((0 << CS12) | (0 << CS11) | (1 << CS10))
869#define TIM1_CLOCK_DIV_8 ((0 << CS12) | (1 << CS11) | (0 << CS10))
871#define TIM1_CLOCK_DIV_64 ((0 << CS12) | (1 << CS11) | (1 << CS10))
873#define TIM1_CLOCK_DIV_256 ((1 << CS12) | (0 << CS11) | (0 << CS10))
875#define TIM1_CLOCK_DIV_1024 ((1 << CS12) | (0 << CS11) | (1 << CS10))
877#define TIM1_CLOCK_EXT_FALLING ((1 << CS12) | (1 << CS11) | (0 << CS10))
879#define TIM1_CLOCK_EXT_RISING ((1 << CS12) | (1 << CS11) | (1 << CS10))
889#define TIM4_PRESCALER_OFF ((0 << CS43) | (0 << CS42) | (0 << CS41) | (0 << CS40))
891#define TIM4_PRESCALER_DIV_1 ((0 << CS43) | (0 << CS42) | (0 << CS41) | (1 << CS40))
893#define TIM4_PRESCALER_DIV_2 ((0 << CS43) | (0 << CS42) | (1 << CS41) | (0 << CS40))
895#define TIM4_PRESCALER_DIV_4 ((0 << CS43) | (0 << CS42) | (1 << CS41) | (1 << CS40))
906#define ADC_MUX_L_BITS ((1 << MUX4) | (1 << MUX3) | (1 << MUX2) | (1 << MUX1) | (1 << MUX0))
908#define ADC_MUX_H_BITS (1 << MUX5)
910#define ADC_MUX_L_ADC0 ((0 << MUX4) | (0 << MUX3) | (0 << MUX2) | (0 << MUX1) | (0 << MUX0))
912#define ADC_MUX_H_ADC0 (0 << MUX5)
914#define ADC_MUX_L_ADC1 ((0 << MUX4) | (0 << MUX3) | (0 << MUX2) | (0 << MUX1) | (1 << MUX0))
916#define ADC_MUX_H_ADC1 (0 << MUX5)
918#define ADC_MUX_L_ADC4 ((0 << MUX4) | (0 << MUX3) | (1 << MUX2) | (0 << MUX1) | (0 << MUX0))
920#define ADC_MUX_H_ADC4 (0 << MUX5)
922#define ADC_MUX_L_ADC5 ((0 << MUX4) | (0 << MUX3) | (1 << MUX2) | (0 << MUX1) | (1 << MUX0))
924#define ADC_MUX_H_ADC5 (0 << MUX5)
926#define ADC_MUX_L_ADC6 ((0 << MUX4) | (0 << MUX3) | (1 << MUX2) | (1 << MUX1) | (0 << MUX0))
928#define ADC_MUX_H_ADC6 (0 << MUX5)
930#define ADC_MUX_L_ADC7 ((0 << MUX4) | (0 << MUX3) | (1 << MUX2) | (1 << MUX1) | (1 << MUX0))
932#define ADC_MUX_H_ADC7 (0 << MUX5)
934#define ADC_MUX_L_ADC8 ((0 << MUX4) | (0 << MUX3) | (0 << MUX2) | (0 << MUX1) | (0 << MUX0))
936#define ADC_MUX_H_ADC8 (1 << MUX5)
938#define ADC_MUX_L_ADC9 ((0 << MUX4) | (0 << MUX3) | (0 << MUX2) | (0 << MUX1) | (1 << MUX0))
940#define ADC_MUX_H_ADC9 (1 << MUX5)
942#define ADC_MUX_L_ADC10 ((0 << MUX4) | (0 << MUX3) | (0 << MUX2) | (1 << MUX1) | (0 << MUX0))
944#define ADC_MUX_H_ADC10 (1 << MUX5)
946#define ADC_MUX_L_ADC11 ((0 << MUX4) | (0 << MUX3) | (0 << MUX2) | (1 << MUX1) | (1 << MUX0))
948#define ADC_MUX_H_ADC11 (1 << MUX5)
950#define ADC_MUX_L_ADC12 ((0 << MUX4) | (0 << MUX3) | (1 << MUX2) | (0 << MUX1) | (0 << MUX0))
952#define ADC_MUX_H_ADC12 (1 << MUX5)
954#define ADC_MUX_L_ADC13 ((0 << MUX4) | (0 << MUX3) | (1 << MUX2) | (0 << MUX1) | (1 << MUX0))
956#define ADC_MUX_H_ADC13 (1 << MUX5)
958#define ADC_MUX_L_TEMP_SENSOR ((0 << MUX4) | (0 << MUX3) | (1 << MUX2) | (1 << MUX1) | (1 << MUX0))
960#define ADC_MUX_H_TEMP_SENSOR (1 << MUX5)
962#define ADC_MUX_L_1V1 ((1 << MUX4) | (1 << MUX3) | (1 << MUX2) | (1 << MUX1) | (0 << MUX0))
964#define ADC_MUX_H_1V1 (0 << MUX5)
966#define ADC_MUX_L_0V ((1 << MUX4) | (1 << MUX3) | (1 << MUX2) | (1 << MUX1) | (1 << MUX0))
968#define ADC_MUX_H_0V (0 << MUX5)
978#define ADC_PRESCALER_DIV_2 ((0 << ADPS2) | (0 << ADPS1) | (0 << ADPS0))
980#define ADC_PRESCALER_DIV_4 ((0 << ADPS2) | (1 << ADPS1) | (0 << ADPS0))
982#define ADC_PRESCALER_DIV_8 ((0 << ADPS2) | (1 << ADPS1) | (1 << ADPS0))
984#define ADC_PRESCALER_DIV_16 ((1 << ADPS2) | (0 << ADPS1) | (0 << ADPS0))
986#define ADC_PRESCALER_DIV_32 ((1 << ADPS2) | (0 << ADPS1) | (1 << ADPS0))
988#define ADC_PRESCALER_DIV_64 ((1 << ADPS2) | (1 << ADPS1) | (0 << ADPS0))
990#define ADC_PRESCALER_DIV_128 ((1 << ADPS2) | (1 << ADPS1) | (1 << ADPS0))
1000#define ADC_REFERENCE_VOLTAGE_AREF ((0 << REFS1) | (0 << REFS0))
1002#define ADC_REFERENCE_VOLTAGE_VCC ((0 << REFS1) | (1 << REFS0))
1004#define ADC_REFERENCE_VOLTAGE_INTERNAL ((1 << REFS1) | (1 << REFS0))
1014#define ADC_TRIGGER_FREE ((0 << ADTS3) | (0 << ADTS2) | (0 << ADTS1) | (0 << ADTS0))
1016#define ADC_TRIGGER_ANALOG_COMP ((0 << ADTS3) | (0 << ADTS2) | (0 << ADTS1) | (1 << ADTS0))
1018#define ADC_TRIGGER_INT0 ((0 << ADTS3) | (0 << ADTS2) | (1 << ADTS1) | (0 << ADTS0))
1020#define ADC_TRIGGER_TIMER0_COMPA ((0 << ADTS3) | (0 << ADTS2) | (1 << ADTS1) | (1 << ADTS0))
1022#define ADC_TRIGGER_TIMER0_OVF ((0 << ADTS3) | (1 << ADTS2) | (0 << ADTS1) | (0 << ADTS0))
1024#define ADC_TRIGGER_TIMER1_COMPB ((0 << ADTS3) | (1 << ADTS2) | (0 << ADTS1) | (1 << ADTS0))
1026#define ADC_TRIGGER_TIMER1_OVF ((0 << ADTS3) | (1 << ADTS2) | (1 << ADTS1) | (0 << ADTS0))
1028#define ADC_TRIGGER_TIMER1_CAPT ((0 << ADTS3) | (1 << ADTS2) | (1 << ADTS1) | (1 << ADTS0))
1030#define ADC_TRIGGER_TIMER4_OVF ((1 << ADTS3) | (0 << ADTS2) | (0 << ADTS1) | (0 << ADTS0))
1032#define ADC_TRIGGER_TIMER4_COMPA ((1 << ADTS3) | (0 << ADTS2) | (0 << ADTS1) | (1 << ADTS0))
1034#define ADC_TRIGGER_TIMER4_COMPB ((1 << ADTS3) | (0 << ADTS2) | (1 << ADTS1) | (0 << ADTS0))
1036#define ADC_TRIGGER_TIMER4_COMPD ((1 << ADTS3) | (0 << ADTS2) | (1 << ADTS1) | (1 << ADTS0))
1144#define TIM4_PRESCALER_DIV_PATTERN(tim4Prescaler) \
1145 ((tim4Prescaler) == 1 ? TIM4_PRESCALER_DIV_1 : (tim4Prescaler) == 2 ? TIM4_PRESCALER_DIV_2 \
1146 : (tim4Prescaler) == 4 ? TIM4_PRESCALER_DIV_4 \
1151#define TIM4_TOP(tim4Freq) (((F_HST / ((uint32_t)tim4Freq * CHOOSE_TIM4_PRESCALER(tim4Freq))) >> 1) - 1)
1154#define TIM4_TOP_MAX 0x03ff
1162#define DT_PRESCALER_DIV_PATTERN(dtPrescaler) \
1163 ((dtPrescaler) == 1 ? DT_PRESCALER_DIV_1 : (dtPrescaler) == 2 ? DT_PRESCALER_DIV_2 \
1164 : (dtPrescaler) == 4 ? DT_PRESCALER_DIV_4 \
1165 : (dtPrescaler) == 8 ? DT_PRESCALER_DIV_8 \
1172#define DEAD_TIME_HALF(deadTime) (((uint8_t)(ceil((double)deadTime * F_HST / ((double)CHOOSE_DT_PRESCALER(deadTime) * 1000000000)))))
1180#define TIM3_TOP (((F_CPU / TIM3_FREQ / 3) >> 4) - 1)
1183#define TIM3_TOP_MAX 0xffff
1184#if TIM3_TOP_ > TIM3_TOP_MAX
1185#error "Invalid TIM3_FREQ set"
1188#if ((EMULATE_HALL == TRUE) && (SPEED_CONTROL_METHOD == SPEED_CONTROL_CLOSED_LOOP))
1189#error "Invalid combination of EMULATE_HALL and SPEED_CONTROL_METHOD"
struct motorflags motorflags_t
Collection of all motor control flags.
fault_flag_t
Enumeration of fault flags.
struct motorconfigs motorconfigs_t
Collection of motor configurations.
struct faultflags faultflags_t
Collection of all fault flags.
@ FAULT_OVER_CURRENT
Has it tripped the over current limit?
@ FAULT_USER_FLAG1
Is user flag 1 set?
@ FAULT_NO_HALL_CONNECTIONS
Is there no hall connections?
@ FAULT_USER_FLAG2
Is user flag 2 set?
@ FAULT_RESERVED
Reserved flag, always false.
@ FAULT_USER_FLAG3
Is user flag 3 set?
@ FAULT_REVERSE_DIRECTION
Is motor spinning in an unexpected direction?
@ FAULT_MOTOR_STOPPED
Is motor stopped?
Collection of all fault flags.
uint8_t userFlag2
Is user flag 2 set?
uint8_t motorStopped
Is motor stopped?
uint8_t userFlag3
Is user flag 3 set?
uint8_t reserved
Reserved bit(s).
uint8_t noHallConnections
Is there no hall connections?
uint8_t overCurrent
Has it tripped the over current limit?
uint8_t reverseDirection
Is motor spinning in an unexpected direction?
uint8_t userFlag1
Is user flag 1 set?
Collection of motor configurations.
uint16_t tim4Top
Corresponding TIM4 top value for TIM4 frequency.
uint8_t speedInputSource
SpeedInput source select (only for remote mode).
uint16_t tim4DeadTime
Corresponding dead time for TIM4 output.
uint32_t tim4Freq
TIM4 or gate switching frequency.
Collection of all motor control flags.
uint8_t desiredDirection
The desired direction of rotation.
uint8_t enable
Is the motor enabled?
uint8_t actualDirection
The actual direction of rotation.
uint8_t driveWaveform
The current waveform that should be produced.
uint8_t fatalFault
Fatal fault.
uint8_t reserved
Reserved bit(s).
uint8_t remote
Is the remote enabled?
uint8_t speedControllerRun
Should speed controller run?